TLC1550I, TLC1550M, TLC1551I10ĆBIT ANALOGĆTOĆDIGITAL CONVERTERSWITH PARALLEL OUTPUTSSLAS043G − MAY 1991 − REVISED NOVEMBER 2003DPower Dissipation...40 mW MaxDAdvanced LinEPIC Single-Poly ProcessDDDDDProvides Close Capacitor Matching forBetter AccuracyFast Parallel Processing for DSP and µPInterfaceEither External or Internal Clock Can BeUsedConversion Time...6 µsTotal Unadjusted Error...±1 LSB MaxCMOS TechnologyJ† OR DW PACKAGE(TOP VIEW) descriptionThe TLC1550x and TLC1551 are data acquisitionanalog-to-digital converters (ADCs) usinga 10-bit,switched-capacitor, successive-approximation net-work. Ahigh-speed, 3-state parallel port directlyinterfaces to a digital signal processor (DSP) ormicroprocessor (µP) system data bus. D0 throughD9 are the digital output terminals with D0 beingthe least significant bit (LSB). Separate powerterminals for the analog and digital portionsminimize noise pickup in the supply leads.Additionally, the digital power is divided into twoparts to separate the lower current logic from thehigher current bus drivers. An external clock can beapplied to CLKIN to override the internal systemclock if desired.The TLC1550I and TLC1551I are characterized foroperation from −40°C to 85°C. The TLC1550M ischaracterized over the full military range of −55°Cto 125°C.REF+REF−ANLG GNDAINANLG VDDDGTL GND1DGTL GND2DGTL VDD1DGTL VDD2EOCD0D11234 567101112242322212019181716151413RDWRCLKINCSD9D8D7D6D5D4D3D2†Refer to the mechanical data for the JWpackage.AINANLG VDDDGTL GND1NCDGTL GND2DGTL VDD1DGTL VDD2ANLG GNDREF−REF+NCRDWRCLKIN567104NC − No internal connectionPACKAGECERAMIC DIP(J)—TLC1550MJ—FK OR FN PACKAGE(TOP VIEW)321282726252423222120111912131415161718CSD9D8NCD7D6D5AVAILABLE OPTIONSTA−40°C to 85°C−55°C to 125°CCERAMIC CHIP CARRIER(FK)—TLC1550MFKPLASTIC CHIP CARRIER(FN)TLC1550IFNTLC1551IFNSOIC(DW)TLC1550IDWTLC1551IDW—This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. Thesecircuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-ratedvoltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the deviceshould be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,preferably either VCC or ground.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Advanced LinEPIC is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•EOCD0D1NCD2D3D4Copyright 2003, Texas Instruments IncorporatedOn products compliant to MILĆPRFĆ38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.1SLAS043G − MAY 1991 − REVISED NOVEMBER 2003TLC1550I, TLC1550M, TLC1551I10ĆBIT ANALOGĆTOĆDIGITAL CONVERTERSWITH PARALLEL OUTPUTSfunctional block diagramEOCCSWRRDControlLogicSuccessive-ApproximationRegister10D0−D910DGTL VDD1100 kΩNOMClock DetectorFrequencyDivided by 2InternalClock10-BitCapacitorDAC and S/HCompCLKINREF+REF−AINtypical equivalent inputsINPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE1 kΩ TYPAINCi = 60 pF TYP(equivalent inputcapacitance)AIN5 MΩ TYPINPUT CIRCUIT IMPEDANCE DURING HOLD MODE2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC1550I, TLC1550M, TLC1551I10ĆBIT ANALOGĆTOĆDIGITAL CONVERTERSWITH PARALLEL OUTPUTSSLAS043G − MAY 1991 − REVISED NOVEMBER 2003Terminal FunctionsTERMINALNAMENO.†ANLG GNDAINANLG VDDCLKIN45626NO.‡34522DESCRIPTIONAnalog ground. The reference point for the voltage applied on terminals ANLG VDD, AIN, REF+, and REF−.Analog voltage input. The voltage applied to AIN is converted to the equivalent digital output.Analog positive power supply voltage. The voltage applied to this terminal is designated VDD3.Clock input. CLKIN is used for external clocking instead of using the internal system clock. It usually takes afew microseconds before the internal clock is disabled. To use the internal clock, CLKIN should be tied highor left unconnected.Chip-select. CS must be low for RD or WR to be recognized by the A/D converter.Data bus output. D0 is bit 1 (LSB).Data bus output. D1 is bit 2.Data bus output. D2 is bit 3.Data bus output. D3 is bit 4.Data bus output. D4 is bit 5.Data bus output. D5 is bit 6.Data bus output. D6 is bit 7.Data bus output. D7 is bit 8.Data bus output. D8 is bit 9.Data bus output. D9 is bit 10 (MSB).Digital ground 1. The ground for power supply DGTL VDD1 and is the substrate connectionDigital ground 2. The ground for power supply DGTL VDD2Digital positive power-supply voltage 1. DGTL VDD1 supplies the logic. The voltage applied to DGTL VDD1 isdesignated VDD1.Digital positive power-supply voltage 2. DGTL VDD2 supplies only the higher-current output buffers. The voltageapplied to DGTL VDD2 is designated VDD2.End-of-conversion. EOC goes low indicating that conversion is complete and the results have been transferredto the output latch. EOC can be connected to the µP- or DSP-interrupt terminal or can be continuously polled.Read input. When CS is low and RD is taken low, the data is placed on the data bus from the output latch. Theoutput latch stores the conversion results at the most recent negative edge of EOC. The falling edge of RDresets EOC to a high within the td(EOC) specifications.Positive voltage-reference input. Any analog input that is greater than or equal to the voltage on REF+ convertsto 1111111111. Analog input voltages between REF+ and REF− convert to the appropriate result in a ratiometricmanner.Negative voltage reference input. Any analog input that is less than or equal to the voltage on REF− convertsto 0000000000.Write input. When CS is low, conversion is started on the rising edge of WR. On this rising edge, the ADC holdsthe analog input until conversion is completed. Before and after the conversion period, which is given by tconv,the ADC remains in the sampling mode.CSD0D1D2D3D4D5D6D7D8D9DGTL GND1DGTL GND2DGTL VDD1DGTL VDD2EOCRD251314161718192021232479101112282111121314151617181920671024REF+21REF−WR327223†Terminal numbers for FK and FN packages.‡Terminal numbers for J, DW, and NW packages.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3SLAS043G − MAY 1991 − REVISED NOVEMBER 2003TLC1550I, TLC1550M, TLC1551I10ĆBIT ANALOGĆTOĆDIGITAL CONVERTERSWITH PARALLEL OUTPUTSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage, VDD1, VDD2, and VDD3 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 VInput voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3 VOutput voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3 VPeak input current (any digital input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mAPeak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mAOperating free-air temperature range, TA: TLC1550I, TLC1551I . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°CTLC1550M −55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°CStorage temperature range, Tstg −65Case temperature for 10 seconds: FK or FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°CLead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: J or NW package . . . . . . . . . . . . 260°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTE 1:VDD1 is the voltage measured at DGTL VDD1 with respect to DGND1. VDD2 is the voltage measured at DGTL VDD2 with respect to theDGND2. VDD3 is the voltage measured at ANLG VDD with respect to AGND. For these specifications, all ground terminals are tiedtogether (and represent 0 V). When VDD1, VDD2, and VDD3 are equal, they are referred to simply as VDD.recommended operating conditionsMINSupply voltage, VDD1, VDD2, VDD3Positive reference voltage, VREF+ (see Note 2)Negative reference voltage, VREF− (see Note 2)Differential reference voltage, VREF+ − VREF− (see Note 2)Analog input voltage rangeHigh-level control input voltage, VIHLow-level control input voltage, VILInput clock frequency, f(CLKIN)Setup time, CS low before WR or RD goes low, tsu(CS)Hold time, CS low after WR or RD goes high, th(CS)WR or RD pulse duration, tw(WR)Input clock low pulse duration, tw(L−CLKIN)Operating free-air temperature, TATLC155xITLC1550M020.80.5005040% ofperiod−40−5580% ofperiod85125°C7.84.75NOM5VDD30VDD3VDD3MAX5.5UNITVVVVVVVMHznsnsnsNOTE 2:Analog input voltages greater than that applied to REF+ convert to all 1s (1111111111), while input voltages less than that applied toREF− convert to all 0s (0000000000). The total unadjusted error may increase as this differential voltage falls below 4.75 V.4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC1550I, TLC1550M, TLC1551I10ĆBIT ANALOGĆTOĆDIGITAL CONVERTERSWITH PARALLEL OUTPUTSSLAS043G − MAY 1991 − REVISED NOVEMBER 2003electrical characteristics over recommended operating free-air temperature range,VDD=VREF+=4.75 V to 5.5 V and VREF− = 0 (unless otherwise noted)PARAMETERVOHVOLIOZIIHIILIILIOSHigh-level output voltageLow-level output voltageOff-state (high-impedance-state) output currentHigh-level input currentLow-level input current (except CLKIN)Low-level input current (CLKIN)Short-circuit output currentVO = 5 V,VO = 0,Analog inputsDigital inputsTA = 25°CTA = 25°CTEST CONDITIONSVDD = 4.75 V,VDD = 4.75 V,IOL = 2.4 mAVO = VDD,VO = 0,VI = VDDVI = 0IOH = −360 µATA = 25°CTA = −55°C to 125°CCS and RD at VDDCS and RD at VDD0.005−2.5−507−0.005−5014−122605−60*15*MIN2.40.40.510−102.5TYP†MAXUNITVVµAµAµAµAmAmApFI(DD)Operating supply currentCiInput capacitanceCS low and RD highSee typical equivalent inputs TLC1550/1I* On products compliant to MIL-STD-883, Class B, this parameter is not production tested.†All typical values are at VDD = 5 V, TA = 25°C.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•5SLAS043G − MAY 1991 − REVISED NOVEMBER 2003TLC1550I, TLC1550M, TLC1551I10ĆBIT ANALOGĆTOĆDIGITAL CONVERTERSWITH PARALLEL OUTPUTSoperating characteristics over recommended operating free-air temperature range with internalclock and minimum sampling time of 4 µs, VDD=VREF+=5 V and VREF− = 0 (unless otherwisenoted)PARAMETERTLC1550IELLinearity errorTLC1551ITLC1550MTLC1550IEZSZero-scale errorTLC1551ITLC1550MTLC1550IEFSFull-scale errorTLC1551ITLC1550MTLC1550ITotal unadjusted errorTLC1551ITLC1550Mtcta(D)tv(D)tdis(D)Conversion timeData access time after RD goes lowData valid time after RD goes highDisable time, delay time from RD high to highimpedanceSee Figure 3530fclock(external) = 4.2 MHz orinternal clockSee Note 5See Notes 2 and 4See Notes 2 and 4See Note 3TEST CONDITIONSTA†Full rangeFull range25°CFull rangeFull rangeFull range25°CFull rangeFull rangeFull range25°CFull rangeFull rangeFull range25°CMINTYP‡MAX±0.5±1±0.5±1±0.5±1±0.5±1±0.5±1±0.5±1±0.5±1±1635µsnsnsnsLSBLSBLSBLSBUNITtd(EOC)Delay time, RD low to EOC high015ns†Full range is −40°C to 85°C for the TL155xI devices and −55°C to 125°C for the TLC1550M.‡All typical values are at VDD = 5 V, TA = 25°C.NOTES:2.Analog input voltages greater than that applied to REF+ convert to all 1s (1111111111), while input voltages less than that appliedto REF− convert to all 0s (0000000000). The total unadjusted error may increase as this differential voltage falls below 4.75 V.3.Linearity error is the difference between the actual analog value at the transition between any two adjacent steps and its ideal valueafter zero-scale error and full-scale error have been removed.4.Zero-scale error is the difference between the actual mid-step value and the nominal mid-step value at specified zero scale.Full-scale error is the difference between the actual mid-step value and the nominal mid-step value at specified full scale.5.Total unadjusted error is the difference between the actual analog value at the transition between any two adjacent steps and itsideal value. It includes contributions from zero-scale error, full-scale error, and linearity error.6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC1550I, TLC1550M, TLC1551I10ĆBIT ANALOGĆTOĆDIGITAL CONVERTERSWITH PARALLEL OUTPUTSSLAS043G − MAY 1991 − REVISED NOVEMBER 2003PARAMETER MEASUREMENT INFORMATIONSource Current = 6 mATest PointOutputUnder TestCL = 62 pFSink Current = 6 mAVcp = voltage commutation point for switching between source and sink currentsNOTE A:Equivalent load circuit of the Teradyne A500 tester for timing parameter measurementSee Note AVcp = 1 VFigure 1. Test Load CircuitPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•7SLAS043G − MAY 1991 − REVISED NOVEMBER 2003TLC1550I, TLC1550M, TLC1551I10ĆBIT ANALOGĆTOĆDIGITAL CONVERTERSWITH PARALLEL OUTPUTSAPPLICATION INFORMATIONsimplified analog input analysisUsing the circuit in Figure 2, the time required to charge the analog input capacitance from 0 to VS within 1/2LSB can be derived as follows:The capacitance charging voltage is given byVWhere:Rt = Rs + riThe final voltage to 1/2 LSB is given byVC (1/2 LSB) = VS − (VS/1024)Equating equation 1 to equation 2 and solving for time tc givesV*Vń512+V1–eSSSandtc (1/2 LSB) = Rt × Ci × ln(1024)Therefore, with the values given, the time for the analog input signal to settle istc (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(1024)This time must be less than the converter sample time shown in the timing diagrams.Driving Source†RsVSri1 kΩ MAXVCCi50 pF MAXTLC1550/1C+V–tńRCǒ1−ectiǓS(1)(2)ǒǓǒ–tcńRtCiǓ(3)(4)(5)VIVI= Input voltage at AINVS= External driving source voltageRs= Source resistanceri= Input resistanceCi= Input capacitance†Driving source requirements:•Noise and distortion for the source must be equivalent to the resolution of the converter.•Rs must be real at the input frequency.Figure 2. Input Circuit Including the Driving Source8POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC1550I, TLC1550M, TLC1551I10ĆBIT ANALOGĆTOĆDIGITAL CONVERTERSWITH PARALLEL OUTPUTSSLAS043G − MAY 1991 − REVISED NOVEMBER 2003PRINCIPLES OF OPERATIONThe operating sequence for complete data acquisition is shown in Figure 3. Processors can address the TLC1550and TLC1551 as an external memory device by simply connecting the address lines to a decoder and the decoderoutput to CS. Like other peripheral devices, the write (WR) and read (RD) input signals are valid only when CS is low.Once CS is low, the onboard system clock permits the conversion to begin with a simple write command and theconverted data to be presented to the data bus with a simple read command. The device remains in a sampling (track)mode from the rising edge of EOC until conversion begins with the rising edge of WR, which initiates the hold mode.After the hold mode begins, the clock controls the conversion automatically. When the conversion is complete, theend-of-conversion (EOC) signal goes low indicating that the digital data has been transferred to the output latch.Lowering CS and RD then resets EOC and transfers the data to the data bus for the processor read cycle.tsu(CS)CSth(CS)0.8 Vtw(WR)0.8 Vtc2 V1.4 V0.8 V0.8 VWR1.4 V0.8 Vtsu(CS)2 Vth(CS)RD0.8 Vta(D)tv(D)2 VData Valid0.8 Vtd(EOC)2 V0.8 Vtdis(D)D0−D9EOC0.8 V2 VFigure 3. TLC1550 or TLC1551 Operating SequencePOST OFFICE BOX 655303 DALLAS, TEXAS 75265•9PACKAGEOPTIONADDENDUM
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PACKAGINGINFORMATION
OrderableDeviceTLC1550IDWTLC1550IDWG4TLC1550IDWRTLC1550IDWRG4TLC1550IFNTLC1550IFNG4TLC1550IFNRTLC1550INWTLC1550MFKBTLC1550MJTLC1550MJBTLC1551IDWTLC1551IDWG4TLC1551IDWRTLC1551IDWRG4TLC1551IFNTLC1551IFNG4
(1)
Status(1)ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEOBSOLETEOBSOLETEOBSOLETEOBSOLETEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE
PackageTypeSOICSOICSOICSOICPLCCPLCCPLCCPDIPLCCCCDIPCDIPSOICSOICSOICSOICPLCCPLCC
PackageDrawingDWDWDWDWFNFNFNNWFKJJDWDWDWDWFNFN
PinsPackageEcoPlan(2)
Qty2424242428282824282424242424242828
25252525
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCallTICallTICallTICallTICUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU
MSLPeakTemp(3)Level-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMCallTICallTICallTICallTI
Level-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIM
2000Green(RoHS&
noSb/Br)2000Green(RoHS&
noSb/Br)3737750
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
TBDTBDTBDTBDGreen(RoHS&noSb/Br)Green(RoHS&noSb/Br)
2000Green(RoHS&
noSb/Br)2000Green(RoHS&
noSb/Br)3737
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)
(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksolder
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PACKAGEOPTIONADDENDUM
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temperature.
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Addendum-Page2
MECHANICAL DATA MLCC006B – OCTOBER 1996FK (S-CQCC-N**) 28 TERMINAL SHOWNLEADLESS CERAMIC CHIP CARRIER18171615141312NO. OFTERMINALS**1110287668584445220AMIN0.342(8,69)0.442(11,23)0.0(16,26)0.739(18,78)0.938(23,83)1.141(28,99)MAX0.358(9,09)0.458(11,63)0.660(16,76)0.761(19,32)0.962(24,43)1.165(29,59)MIN0.307(7,80)0.406(10,31)0.495(12,58)0.495(12,58)0.850(21,6)1.047(26,6)BMAX0.358(9,09)0.458(11,63)0.560(14,22)0.560(14,22)0.858(21,8)1.063(27,0)192021B SQ22A SQ23242526272812340.080 (2,03)0.0 (1,63)0.020 (0,51)0.010 (0,25)0.020 (0,51)0.010 (0,25)0.055 (1,40)0.045 (1,14)0.045 (1,14)0.035 (0,)0.028 (0,71)0.022 (0,54)0.050 (1,27)0.045 (1,14)0.035 (0,)4040140/D 10/96NOTES:A.B.C.D.E.All linear dimensions are in inches (millimeters).This drawing is subject to change without notice.This package can be hermetically sealed with a metal lid.The terminals are gold plated.Falls within JEDEC MS-004POST OFFICE BOX 655303 DALLAS, TEXAS 75265• MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997 MECHANICAL DATA J (R-GDIP-T**) 24 PINS SHOWNB2413CERAMIC DUAL-IN-LINE PACKAGEC10.065 (1,65)0.045 (1,14)0.090 (2,29)0.060 (1,53)12Lens Protrusion (Lens Optional)0.010 (0.25) MAX0.175 (4,45)0.140 (3,56)ASeating Plane0.018 (0,46) MIN0.022 (0,56)0.014 (0,36)0.125 (3,18) MIN0.012 (0,30)0.008 (0,20)28WIDENARRWIDENARR32WIDENARR40WIDE0.100 (2,54)PINS **DIM”A”MAXMINMAXMINMAXMINNARR240.624(15,85) 0.624(15,85)0.624(15,85) 0.624(15,85)0.624(15,85) 0.624(15,85)0.624(15,85) 0.624(15,85)0.590(14,99) 0.590(14,99)0.590(14,99) 0.590(14,99)0.590(14,99) 0.590(14,99)0.590(14,99) 0.590(14,99)1.265(32,13) 1.265(32,13)1.465(37,21) 1.465(37,21)1.668(42,37) 1.668(42,37)2.068(52,53) 2.068(52,53)1.235(31,37) 1.235(31,37)1.435(36,45) 1.435(36,45)1.632(41,45) 1.632(41,45)2.032(51,61) 2.032(51,61)0.541(13,74) 0.598(15,19)0.541(13,74) 0.598(15,19)0.541(13,74) 0.598(15,19)0.541(13,74) 0.598(15,19)0.514(13,06) 0.571(14,50)0.514(13,06) 0.571(14,50)0.514(13,06) 0.571(14,50)0.514(13,06) 0.571(14,50)4040084/C 10/97”B””C”NOTES:A.B.C.D.E.All linear dimensions are in inches (millimeters).This drawing is subject to change without notice.Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin).This package can be hermetically sealed with a ceramic lid using glass frit.Index point is provided on cap for terminal identification.POST OFFICE BOX 655303 DALLAS, TEXAS 75265• MECHANICAL DATA MPLC004A – OCTOBER 1994FN (S-PQCC-J**) 20 PIN SHOWNPLASTIC J-LEADED CHIP CARRIERSeating Plane0.004 (0,10)DD131190.032 (0,81)0.026 (0,66)418D2/E20.180 (4,57) MAX0.120 (3,05)0.090 (2,29)0.020 (0,51) MINEE1D2/E28149130.050 (1,27)0.008 (0,20) NOM0.021 (0,53)0.013 (0,33)0.007 (0,18)MNO. OFPINS**202844526884D/EMIN0.385 (9,78)0.485 (12,32)0.685 (17,40)0.785 (19,94)0.985 (25,02)1.185 (30,10)MAX0.395 (10,03)0.495 (12,57)0.695 (17,65)0.795 (20,19)0.995 (25,27)1.195 (30,35)MIND1/E1MAX0.356 (9,04)0.456 (11,58)0.656 (16,66)0.756 (19,20)0.958 (24,33)1.158 (29,41)MIND2/E2MAX0.169 (4,29)0.219 (5,56)0.319 (8,10)0.369 (9,37)0.469 (11,91)0.569 (14,45)4040005/B 03/950.350 (8,)0.450 (11,43)0.650 (16,51)0.750 (19,05)0.950 (24,13)1.150 (29,21)0.141 (3,58)0.191 (4,85)0.291 (7,39)0.341 (8,66)0.441 (11,20)0.541 (13,74)NOTES:A.All linear dimensions are in inches (millimeters).B.This drawing is subject to change without notice.C.Falls within JEDEC MS-018POST OFFICE BOX 655303 DALLAS, TEXAS 75265•1IMPORTANTNOTICE
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